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ADT7475
16-bit Limits
The fan TACH measurements are 16-bit results. The fan
TACH limits are also 16 bits, consisting of a high byte and
low byte. Because fans running under speed or stalled are
normally the only conditions of interest, only high limits
exist for fan TACHs. Because the fan TACH period is
actually being measured, exceeding the limit indicates a
slow or stalled fan.
Table 23. FAN LIMIT REGISTERS
of interest, because the most recently measured value of any
input can be read out at any time.
For applications where the monitoring cycle time is
important, it can easily be calculated. The total number of
channels measured is
? One Dedicated Supply Voltage Input (V CCP Pin)
? Supply Voltage (V CC Pin)
? Local Temperature
? Two Remote Temperatures
Register
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
Description
TACH1 Minimum Low Byte
TACH1 Minimum High Byte
TACH2 Minimum Low Byte
TACH2 Minimum High Byte
TACH3 Minimum Low Byte
TACH3 Minimum High Byte
TACH4 Minimum Low Byte
TACH4 Minimum High Byte
Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged
voltage and temperature monitoring is 146 ms. The total
monitoring cycle time for voltage and temperature
monitoring with averaging disabled is 19 ms. The
ADT7475 is a derivative of the ADT7467. As a result, the
total conversion time in the ADT7475 is the same as the total
conversion time of the ADT7467.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7475 can
be enabled for monitoring. The ADT7475 measures all
voltage and temperature measurements in round-robin
format and sets the appropriate status bit for out-of-limit
conditions. TACH measurements are not part of this
round-robin cycle. Comparisons are done differently,
depending on whether the measured value is being
compared to a high or low limit.
High Limit > Comparison Performed
Low Limit ≤ Comparison Performed
Voltage and temperature channels use a window
comparator for error detecting and, therefore, have high and
low limits. Fan speed measurements use only a low limit.
This fan limit is needed only in manual fan control mode.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0) of Configuration Register 1 (0x40).
By default, the ADT7475 powers up with this bit set. The
ADC measures each analog input in turn and, as each
measurement is completed, the result is automatically
stored in the appropriate value register. This round-robin
monitoring cycle continues unless disabled by writing a 0 to
Bit 0 of Configuration Register 1.
As the ADC is normally left to free-run in this manner, the
time taken to monitor all the analog inputs is normally not
Interrupt Status Registers
The results of limit comparisons are stored in Interrupt
Status Register 1 and Interrupt Status Register 2. The status
register bit for each channel reflects the status of the last
measurement and limit comparison on that channel. If a
measurement is within limits, the corresponding status register
bit is cleared to 0. If the measurement is out-of-limits, the
corresponding status register bit is set to 1.
The state of the various measurement channels can be
polled by reading the status registers over the serial bus. In
Bit 7 (OOL) of Interrupt Status Register 1 (0x41), 1 means
that an out-of-limit event has been flagged in Interrupt
Status Register 2. This means that the user needs only to read
Interrupt Status Register 2 when this bit is set. Alternatively,
Pin 5 or Pin 9 can be configured as an SMBALERT output.
This automatically notifies the system supervisor of an
out-of-limit condition. Reading the status registers clears the
appropriate status bit as long as the error condition that
caused the interrupt has cleared.
Status register bits are sticky. Whenever a status bit is set,
indicating an out-of-limit condition, it remains set even if the
event that caused it has gone away (until read). The only way
to clear the status bit is to read the status register after the
event has gone away. Interrupt status mask registers (0x74
and 0x75) allow individual interrupt sources to be masked
from causing an SMBALERT. However, if one of these
masked interrupt sources goes out-of-limit, its associated
status bit is set in the interrupt status registers.
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